In contrast to traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs), which are fabricated using conventional lithographic fabrication methods, nonplanar MOSFETs incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor device is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
A FinFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed in part in a thin fin that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, so a wide channel, and hence high performance, can be achieved without consuming a relatively large area of the substrate surface required by the transistor.
FinFET semiconductor devices often are fabricated using semiconductor (or silicon) on insulator (SOI) substrates. There are significant advantages, however, to fabricating FinFET semiconductor devices on a bulk semiconductor substrate, including significantly lower cost of fabrication and higher crystalline quality of the bulk semiconductor substrate compared to a SOI substrate. Some problems that are easily solved when using SOI substrates must be addressed when fabricating FinFET semiconductor devices on a bulk semiconductor substrate. One of those problems involves electrical isolation between adjacent fins and between adjacent active areas. When using a SOI substrate, electrical isolation between fins is achieved by etching away all of the semiconductor material between the fins, leaving the fins extending upwardly from the underlying insulating material. Fabrication of FinFET semiconductor devices on bulk semiconductor substrates, however, requires the formation of insulator filled trenches, commonly referred to as shallow trench isolation (STI) features.
As semiconductor devices are scaled smaller and smaller, it becomes more difficult to fabricate the STI features between increasingly narrow trenches. For example, with smaller spacing between fins, the prevalence of “seams” or “voids,” which are essentially open spaces in an otherwise continuous material layer, increases as it becomes more difficult to deposit the isolation material between the fins. If the isolation feature contains any such defects, there is a possibility that electrical isolation between transistors may not be provided as desired, potentially resulting in a device failure. Prior art solutions have attempted to employ more “flowable” isolation materials, such as flowable silicon oxides, that are less susceptible to forming seams or voids. However, these flowable materials have an undesirable side effect of causing excess stresses on the fin structures, which can cause fin bending and degraded fin performance.
Accordingly, it is desirable to provide methods for fabricating FinFET integrated circuits on bulk semiconductor substrates that provide the necessary electrical isolation between fin structures. It is further desirable to provide such methods that are not susceptible to fin bending. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.